Data processing system having end-to-end error correction and method therefor

ABSTRACT

In a data processing system having a plurality of error coding function circuitries, a method includes receiving an address which indicates a first storage location for storing a first data value; using a first portion of the address to select one of the plurality of error coding function circuitries as a selected error coding function circuitry; and using the selected error coding function circuitry to generate a first checkbit value, wherein the selected error coding function circuitry uses the first data value to generate the first checkbit value. When the first portion of the address has a first value, a first one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry. When the first portion of the address has a second value, a second one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application is a divisional of U.S. application Ser. No.12/880,352, filed on Sep. 13, 2010, entitled “Data Processing SystemHaving End-to-End Error Correction and Method Therefor,” the entirety ofwhich is incorporated herein by reference.

BACKGROUND

1. Field

This disclosure relates generally to data processing, and morespecifically, to a data processing system having end-to-end errorcorrection and method therefor.

2. Related Art

A memory system may use error correction code (ECC) to detect andcorrect errors in stored data. End-to-end ECC provides error detectioncapabilities from one end of an information transfer structure, througha temporary storage component, to another end of the informationtransfer structure. End-to-end ECC generates error protection codes atthe source of the data transfer. When a memory write operation isinitiated by a bus master, the data and error protection codes arestored in the temporary storage component. At the other end of thetransfer, data integrity is checked using the previously stored errorprotection codes.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and is notlimited by the accompanying figures, in which like references indicatesimilar elements. Elements in the figures are illustrated for simplicityand clarity and have not necessarily been drawn to scale.

FIG. 1 illustrates, in block diagram form, a data processing system inaccordance with an embodiment.

FIG. 2 illustrates a portion of a cache control circuit of the dataprocessing system of FIG. 1 in accordance with one embodiment.

FIG. 3 illustrates a portion of a cache control circuit of the dataprocessing system of FIG. 1 in accordance with another embodiment.

FIG. 4 illustrates a portion of a memory of the data processing systemin accordance with an embodiment.

FIG. 5 illustrates a 64-bit data checkbit generation table in accordancewith an embodiment.

FIG. 6 illustrates a 32-bit data checkbit generation table in accordancewith an embodiment.

FIG. 7 illustrates a 32-bit data checkbit generation table in accordancewith another embodiment.

FIG. 8 illustrates an address portion of a checkbit generation table inaccordance with an embodiment.

FIG. 9 illustrates a cache index address portion of a checkbitgeneration table in accordance with an embodiment.

DETAILED DESCRIPTION

Generally, there is provided, an end-to-end ECC scheme that transformsan ECC granularity from 64 bits of data code to 32 bits in an efficientmanner. A transformation table is generated for the full 64-bitgranularity based on an ECC H-matrix algorithm. The particular tablesused for 32-bit granularity are selected to be subsets of the 64-bittable. This provides a relatively straightforward and efficient ECCtransformation between 64 bits of data and 32 bits of data.

To provide address error detection when accessing cache or other memoryarrays, addressing information is combined with the data information tocompose a combined ECC codeword which is stored in the cache or memory.Such a combined codeword is capable of detecting not only errors in thestored data, but also certain addressing errors or failures, such asaccessing a cache location that is different from the intended locationdue to a hardware error. Such accesses in conventional error codingschemes would not typically be detected, because a valid codeword wouldbe read from the cache, albeit from an unintended address location.Because a given cache entry can store data corresponding to multipledifferent addresses based on the cache TAG value, the address portion ofthe cache coding scheme is a function of the cached address. Thisaddress is typically a physical address that is only obtained afterperforming address translation through a memory management unit (MMU).The coding scheme of the described embodiment alters the addresscomponent from a 29-bit doubleword memory address to a smaller cachearray index address. Using the cache index address instead of the cacheTAG value for address error detection is faster because no MMU lookup isinvolved and the cache index is available early in the cache lookupprocess.

In one aspect, there is provided, in a data processing system having aplurality of error coding function circuitries, each implementing adifferent coding function, a method for generating a checkbit value, themethod comprising: receiving an address which indicates a first storagelocation for storing a first data value; using a first portion of theaddress to select one of the plurality of error coding functioncircuitries as a selected error coding function circuitry, wherein: whenthe first portion of the address has a first value, selecting a firstone of the plurality of error coding function circuitries as theselected error coding function circuitry, and when the first portion ofthe address has a second value, different from the first value,selecting a second one of the plurality of error coding functioncircuitries as the selected error coding function circuitry; and usingthe selected error coding function circuitry to generate a firstcheckbit value, wherein the selected error coding function circuitryuses the first data value to generate the first checkbit value. Theselected error coding function circuitry may use the first data valueand a second portion of the address to generate the first checkbitvalue. The first portion of the address may be further characterized asa more significant portion of the address than the second portion of theaddress. The second portion of the address may not include the firstportion of the address. The method may further comprise storing thefirst data value and the first checkbit value. The method may furthercomprise: receiving a second address which indicates a second storagelocation for storing a second data value; using a first portion of thesecond address to select another one of the plurality of error codingfunction circuitries as a second selected error coding functioncircuitry; using the second selected error coding function circuitry togenerate a second checkbit value, wherein the second selected errorcoding function circuitry uses the second data value to generate thesecond checkbit value; storing the second data value and the secondcheckbit value; accessing the stored first data value, first checkbitvalue, second data value, and second checkbit value; transforming thefirst checkbit value and the second checkbit value into a third checkbitvalue which has a granularity to cover both the first and the seconddata value; and storing the first data value concatenated with thesecond data value and the third checkbit value in a third storagelocation. The method may further comprise transferring the first datavalue concatenated with a second data value over a system interconnectand using the third checkbit value to perform end to end error detectionof the first data value concatenated with a second data value. The stepof transforming may comprise performing a bit-wise exclusive OR of thefirst checkbit value with the second checkbit value to obtain the thirdcheckbit value. The step of transforming may comprise: performing abit-wise exclusive OR of the first checkbit value with the secondcheckbit value to obtain a fourth checkbit value based on the first datavalue concatenated with the second data value; providing a secondportion of the address to address error coding function circuitry togenerate a fifth checkbit value based on the second portion of theaddress; and performing a bit-wise exclusive OR of the fourth checkbitvalue with the fifth checkbit value to obtain the third checkbit value.

In another aspect, there is provided, in a data processing system havinga processor and a memory coupled to the processor via a systeminterconnect, a method comprising: initiating a read operation of amemory location; in response to the initiating the read operation,receiving a first data value and a first checkbit value corresponding tothe first data value from the memory location, wherein the first datavalue comprises a first data value portion and a second data valueportion, each of the first and second data value portions having fewerbits than the first data value; providing the first checkbit value tofirst transforming circuitry and to second transforming circuitry,wherein the first transforming circuitry generates a second checkbitvalue corresponding to the first data value portion and the secondtransforming circuitry generates a third checkbit value corresponding tothe second data value portion; and storing the first data value portionwith the second checkbit value in a first storage location and storingthe second data value portion with the third checkbit value in a secondstorage location. The method may further comprise: accessing the firstdata value portion and the second checkbit value; and using the secondcheckbit value and not the first checkbit value to check the first datavalue portion. The method may further comprise, in response to the stepof initiating the read operation, the memory providing the first datavalue and the second checkbit value to the processor via the systeminterconnect; and after the step of receiving the first data value andthe second checkbit value and prior to the step of providing the firstchecking value to the first transforming circuitry and the secondtransforming circuitry, performing, by the processor, end to end errordetection by using the first checkbit value to check the first datavalue. Each of the first and second storage locations may be locatedwithin a cache memory of the processor and the memory location islocated in the memory, and wherein the step of initiating the readoperation is performed in response to a cache miss or a cache fill. Thefirst transforming circuitry may use system error coding functioncircuitry for generating a checkbit value for an N-bit data value, firstinternal error coding function circuitry for generating a checkbit valuefor an M-bit data value, and cache index error coding function circuitryfor generating a checkbit value for a cache index of the cache, thesecond transforming circuitry may use the system error coding functioncircuitry, second internal error coding function circuitry forgenerating a checkbit value for the M-bit data value, and the cacheindex error coding function circuitry, and the second internal errorcoding function circuitry may implement a different coding function thanthe first internal error coding function and N is greater than M, thefirst data value being an N-bit data value and each of the first andsecond data value portions being the M-bit data value. The firsttransforming circuitry may use system error coding function circuitryfor generating a checkbit value for an N-bit data value and firstinternal error coding function circuitry for generating a checkbit valuefor an M-bit data value, the second transforming circuitry may use thesystem error coding function circuitry and second internal error codingfunction circuitry for generating a checkbit value for an M-bit datavalue, and the second internal error coding function circuitry mayimplement a different coding function that the first internal errorcoding function and N is greater than M, the first data value being anN-bit data value and each of the first and second data value portionsbeing an M-bit data value. The system error coding function circuitrymay comprise a first plurality of exclusive OR (XOR) gates, wherein eachXOR gate of the first plurality of XOR gates outputs one correspondingbit value of the first checkbit value, and wherein each XOR gate of thefirst plurality of XOR gates receives a predetermined subset of bitvalues of the first data value; the first internal error coding functioncircuitry may comprise a second plurality of XOR gates, wherein each XORgate of the second plurality of XOR gates outputs one corresponding bitvalue of the third checkbit value, and wherein each XOR gate of thesecond plurality of XOR gates receives a predetermined subset of bitvalues of the second data value portion; and the second internal errorcoding function circuitry may comprise a third plurality of XOR gates,wherein each XOR gate of the third plurality of XOR gates outputs onecorresponding bit value of the second checkbit value, and wherein eachXOR gate of the third plurality of XOR gates may receive a predeterminedsubset of bit values of the first data value portion.

In yet another aspect, there is provided, in a data processing systemhaving a processor and a memory coupled to the processor via a systeminterconnect, a method comprising: accessing a cache of the processor toaccess a first storage location and an adjacent second storage location,wherein the first storage location comprises a first data value and afirst checkbit value corresponding to the first data value and thesecond storage location comprises a second data value and a secondcheckbit value corresponding to the second data value; transforming thefirst checkbit value and the second checkbit value into a third checkbitvalue which has a granularity to cover the first data value combinedwith the second data value; and storing the first data valueconcatenated with the second data value and the third checkbit value ina storage location of the memory. The method may further comprise:transferring the first data value concatenated with the second datavalue over the system interconnect from the memory to the processor; andusing the third checkbit value to perform end to end error detection ofthe first data value concatenated with the second data value. The stepof transforming may comprise: performing a bit-wise exclusive OR (XOR)of the first checkbit value with the second checkbit value to obtain thethird checkbit value. The step of transforming comprises: performing abit-wise XOR of the first checkbit value with the second checkbit valueto obtain a fourth checkbit value based on the first data valueconcatenated with the second data value; providing a second portion ofthe address to address error coding function circuitry to generate afifth checkbit value based on the second portion of the address; andperforming a bit-wise exclusive OR of the fourth checkbit value with thefifth checkbit value to obtain the third checkbit value.

As used herein, the term “bus” is used to refer to a plurality ofsignals or conductors which may be used to transfer one or more varioustypes of information, such as data, addresses, control, or status. Theconductors as discussed herein may be illustrated or described inreference to being a single conductor, a plurality of conductors,unidirectional conductors, or bidirectional conductors. However,different embodiments may vary the implementation of the conductors. Forexample, separate unidirectional conductors may be used rather thanbidirectional conductors and vice versa. Also, plurality of conductorsmay be replaced with a single conductor that transfers multiple signalsserially or in a time multiplexed manner. Likewise, single conductorscarrying multiple signals may be separated out into various differentconductors carrying subsets of these signals. Therefore, many optionsexist for transferring signals.

The terms “assert” or “set” and “negate” (or “deassert” or “clear”) areused herein when referring to the rendering of a signal, status bit, orsimilar apparatus into its logically true or logically false state,respectively. If the logically true state is a logic level one, thelogically false state is a logic level zero. And if the logically truestate is a logic level zero, the logically false state is a logic levelone.

FIG. 1 illustrates, in block diagram form, a simplified view of dataprocessing system 10 in accordance with an embodiment. Data processingsystem 10 includes processor 11, interconnect 15, slave 16, and memory17. Processor 11 includes processing circuitry 12, cache control circuit13, cache 14, ECC checkbit generation circuit 20, transaction addressqueue 22, ECC error correction 24, and latches 26-29. Memory 17 includescontrol circuit 34, bus interface unit (BIU) 36, and memory array 38.Memory array 38 includes a plurality of multi-bit entries. Entry 40 is arepresentative entry and includes a multi-bit checkbit portion 42 and amulti-bit data portion 44, where the checkbit portion 42 corresponds tothe multi-bit data portion 44. In one embodiment, data processing system10 is a system-on-a-chip (SoC). In one embodiment, processing circuitry12 is a bus master and may be a central processing unit (CPU) or coreand may include a load/store unit, an instruction fetch unit, and one ormore execution units. In another embodiment, processing circuitry 12 maybe a different type of bus master.

Processing circuitry 12 has an output for providing a plurality ofaddress signals labeled “ADDRESS[0:Y]”, wherein Y is an integer, and anoutput for providing a plurality of data signals labeled “DATA”. Cachecontrol circuit 13 has an input for receiving address ADDRESS[0:Y], aninput for receiving data signals DATA, an input for receiving datasignals labeled “DATA IN” from ECC error correction circuit 24, an inputfor receiving error signals labeled “ERROR INFORMATION” from ECC errorcorrection circuit 24, an output connected to latch 28 for providingaddress signals “ADDR”, and an output connected to latch 29 forproviding write data “WDATA”. Cache 14 is bi-directionally coupled tocache control circuit 13. ECC error correction circuit 24 also includesan input connected to latch 26 for receiving read data signals labeled“RDATA”, and an input connected to latch 27 for receiving read checkbitslabeled “RCHKBIT”. Transaction address queue 22 has an input coupled toreceive address ADDR, and an output coupled to an input of ECC errorcorrection circuit 24. ECC checkbit generation circuit 20 has an inputfor receiving address ADDR, an input for receiving write data WDATA, andan output connected to latch 29 for providing write checkbits labeled“WCHKBIT”. System interconnect 20 is provided for coupling one or moreslave devices to processor 11. In FIG. 1, representative slave devicesinclude slave device 16 and memory 17. System interconnect 15 caninclude any type of interconnect circuitry such as for example, across-bar switch or combinational logic. System interconnect circuit 15has an output connected to latch 26 for providing read data RDATA, anoutput connected to latch 27 for providing read checkbits RCHKBIT, aninput connected to latch 28 for receiving address ADDR, an inputconnected to latch 29 for receiving write data WDATA, an input connectedto latch 29 for receiving write checkbits WCHBIT. In memory 17, businterface unit (BIU) 36 is provided for interfacing memory 17 withcircuitry external to memory 17. BIU 36 is bi-directionally connected tosystem interconnect 15 and to control circuit 34. Memory array 38includes a plurality of memory cells for storing data. The memory cellscan be of any type, including volatile and/or non-volatile memory cells.The memory cells are organized as entries, such as entry 40, where eachentry includes a plurality of bits. Entry 40 includes a checkbit portion42 and a data portion 44. Entry 40 may include other portions notillustrated in FIG. 1. In one embodiment, data portion 44 stores a64-bit “doubleword” composed of an even and an odd 32-bit word. Checkbitportion 42 may store a single checkbit value for the 64 bits of data, ormay store separate checkbit portions for each 32-bit word, depending onthe particular embodiment. Control circuit 34 is bi-directionallyconnected to both BIU 36 and memory array 38. Control circuit 34controls read and write access operations to memory array 38.

In data processing systems having cache memory, an ECC granularity of64-bits of data has been adopted because 64 bits is the basic transferwidth of an internal interconnect and is also the natural data width forcache line transfers. In addition, a 29-bit address component isincluded in order to support the end-to-end address checking function.However, the 64-bit plus 29-bit ECC granularity may not be optimal for adata processor because a majority of data accesses are 32 bits wide. A64-bit data granularity would require a read-modify-write operation inthe data cache for every 32-bit data write access, which is asignificant performance penalty. However, a 64-bit data granularity isacceptable for an instruction cache where the only write operations areline-fills consisting of 64-bit doublewords. A checkbit generation tablefor 64-bit granularity is illustrated in FIG. 5. For 32-bit dataaccesses a subset of the 64-bit ECC table is used as illustrated in FIG.6 and FIG. 7. Errors that occur within system interconnect 15 will causeerrors, such as an incorrect address, incorrect write data, or incorrectread data to be provided to a slave device or back to the master(processor 11). Errors occurring within memory 17 will manifestthemselves eventually in the read data RDATA or read checkbits RCHKBITreturned to processor 11. Errors in an address, such as an address tocache 14 or memory 17, are checked using the circuitry illustrated belowin FIG. 2 and an ECC address table illustrated in FIG. 8.

For a write cycle of data processing system 10, internal write addressADDR and internal write data WDATA are sent to checkbit generation logic20 to generate a set of 8 checkbits using the encoding shown in TABLE Sof FIG. 5 for 64-bit ECC granularity. For partial width write operationsthat are less than the entire 64-bit granularity of the ECC code, suchas for a 16-bit or 32-bit data write, the checkbits are calculated basedon what values will be driven on the write data WDATA outputs,regardless of whether the particular byte lanes of the WDATA outputscontain active data. The bus transfer takes place with the write dataWDATA and the write checkbits WCHKBIT flowing to the addressed slave(slave 16 or memory 17) through system interconnect 15. The checkbitsWCHKBIT are used by the slave device to recover the data and addressinformation from the bus, performing any error checking and correctionactions, then regenerating a new set of checkbits to be stored in theaddressed location by merging the partial width write data with existingdata in a read-modify-write operation which generates a new set ofcheckbits to be stored. If the write operation is a full-width writeoperation with full-width ECC granularity, that is a 64-bit writeoperation, then the error checking and corrections may become optional,because any errors will be checked at a later time when the data isre-accessed, thus no regeneration of checkbit information by the slaveis required, and in fact may not be desired due to timing delays andother performance factors. The addressed slave device 16 or memory 17stores the received or regenerated checkbits and the write data (WDATA)into the addressed storage location.

For a read cycle of data processing system 10, the internal read addressADDR is sent to the address portion of the external interface tointerconnect 15 via ADDR output latch 28, and also to transactionaddress queue 22 for eventual use by ECC error correction circuit 24.ECC error correction circuit 24 generates a partial syndrome vector fromthe current outstanding access address based on the address portion ofTABLE S in FIG. 5. This portion can be calculated prior to the read databeing returned to the bus. The bus transfer is initiated with theaddress flowing to the addressed slave device 16 or memory 17 throughsystem interconnect 15. Slave 16 or memory 17 returns the data locatedat the address received by slave 16 or memory 17 without needing toperform any error checking or correction. If the read operation is apartial width read operation of less than the 64-bit width of the systeminterconnect bus RDATA, the slave device still drives full 64-bit ECCgranularity read data and the corresponding set of checkbits. Thecheckbits are representative of the address received by the slave deviceand the returned data. ECC error correction circuit 24 completes thesyndrome bit generation based on the read data RDATA and read checkbitsRCHKBIT information, and detects/corrects any errors in the receivedinformation. If any error has been introduced in the data due to anerror in signaling via the system interconnect 15 either on a previouswrite that updated data in the slave device, or the read transactionbeing driven to the slave due to an addressing error in the memory atthe slave, or due to an error in one or more storage cells of the slave,it is detected and corrected if possible. Corrected data is thenprovided to cache control 13 for storage in cache 14 and use byprocessor circuitry 12. If the syndrome generated by ECC errorcorrection circuit 24 indicates an address bit in error, no correctionis performed and an exception is generated because the data does notcorrespond to the requested address, thus the error is not correctable.For cacheable accesses, the corrected data is used to generate a new setof checkbits, and the corrected data and new checkbits are then storedinto the cache 14.

The illustrated embodiment uses either full granularity (64-bit) errorcorrection codes or a reduced, or partial, granularity of 32-bit codes.Protection of a 64-bit data element and 29 address bits use 8 checkbits.Protection of 32 data bits and 29 address bits also uses 8 checkbits,with a subset encoding scheme. The specific coding used is illustratedin the tables of FIG. 5, FIG. 6, FIG. 7, and FIG. 8. The tables of FIG.6 and FIG. 7 use 32-bit granularity and are selected to be subsets ofthe 64-bit table of FIG. 5. The tables were created using the HsiaoSECDED (single error correction, double error detection) algorithm. Inother embodiments, the tables may be created using another ECCalgorithm, such as for example, Hamming codes, Reed-Solomon, or BCH. Thevarious error coding functions illustrated in FIG. 2, FIG. 3, and FIG. 4and described below can be used together or separately in differentembodiments.

FIG. 2 illustrates a portion of a cache control circuit 13 of the dataprocessing system of FIG. 1 in accordance with one embodiment. Theportion of cache control circuit 13 implements a plurality of errorcoding functions for address and data error detection. For example, theportion of cache control circuit 13 includes error coding functioncircuitry 44, 46, and 48, and multiplexer 50. Error coding functioncircuit 44 implements an error coding function 0, error coding functioncircuit 46 implements an error coding function 1, and error codingfunction circuitry 48 implements error coding function N, where N is aninteger. In one embodiment, only two of the error coding functions ofFIG. 2 are used; error coding function circuit 44 implements the ECCtable illustrated in FIG. 6 and error coding function circuit 46implements the ECC table illustrated in FIG. 7. Each error codingfunction circuit 44, 46, and 48 has two inputs. One input is forreceiving address portion ADDRESS [0:X], and the other input is forreceiving data DATA from processor circuit 12. In the illustratedembodiment, X is 28. In another embodiment, X can be any integer.Address portion ADDRESS [X+1:Y] is provided to a control input ofmultiplexer 50, where Y is any integer greater than X. In theillustrated embodiment, Y is bit number 29. An input of multiplexer 50is connected to an output of each of error coding function circuitry 44,46, and 48. In response to the address and data inputs, multiplexer 50selects one of the error coding functions dependent on address bit 29and provides a checkbit value having 32-bit ECC granularity.

In one embodiment, the address A[0:29] indicates a first storagelocation for storing a first data value. A first portion of the addressis used to select one of the plurality of error coding functioncircuits. The first portion of the address in the illustrated embodimentis address bit A[29]. When the first portion of the address has a firstvalue, a first one of the plurality of error coding function circuits isselected. The table of FIG. 6 is selected when A[29] is equal to a logiczero. When the first portion of the address has a second value differentfrom the first value, a second one of the plurality of error codingfunction circuits is selected. The table of FIG. 7 is selected as thecoding function when A[29] is a logic one. In one embodiment, theselected error coding function uses the first data value and a secondportion of the address A[0:28] to generate a first checkbit value.

FIG. 3 illustrates a portion of cache control circuit 13 of the dataprocessing system of FIG. 1 in accordance with another embodiment. Theportion of cache control circuit 13 implements a plurality of errorcoding functions, including error coding transform functions 54 and 56,to transform 64-bit granularity checkbit values to 32-bit granularitycheckbit values. Each of error coding functions 54 and 56 has an inputfor receiving read data RDATA, and an input for receiving read checkbitsRCHKBIT. Transform function 54 has an output for providing checkbitvalue CACHE CHKBIT 0 and transform function 56 has an output forproviding checkbit value CACHE CHKBIT 1.

A read operation is initiated in a memory location of memory 17. Theread operation may be initiated in response to a cache-miss or a cachelinefill operation. In response to the read operation, a first datavalue RDATA and a first checkbit value RCHKBIT corresponding to theRDATA value are received. The first data value RDATA comprises a firstdata value portion and a second data value portion. The first data valueportion is an even word portion of the memory location corresponding toaddress bit A[29] being a logic zero, and the second data value portionis an odd word portion of the memory location corresponding to addressbit A[29] being a logic one. The first data value RDATA may comprises a64-bit doubleword and the first and second data value portion are 32-bitwords. The first checkbit value RCHKBIT is provided to the firsttransforming circuit 54 and to the second transforming circuit 56. Thefirst transforming circuit 54 generates a second checkbit value CACHECHKBIT 0 corresponding to the first data value portion of RDATA. Thesecond transforming circuit 56 generates a third checkbit value CACHECHKBIT 1 corresponding to the second data value portion (odd word ofRDATA). The first data value portion (even word of RDATA) is stored withthe second checkbit value CACHE CHKBIT 0 in a first storage location ofcache memory 14 and the second data value portion (odd word of RDATA) isstored with the third checkbit value CACHE CHKBIT 1 in a second storagelocation of cache memory 14. The even and odd word portions areillustrated in FIG. 4. When the first data value portion and the secondcheckbit value are accessed, the first data value portion is checkedusing the second checkbit value because the second checkbit value onlycovers 32 bits of data. If the first data value portion in the cache issubsequently accessed for a read operation, the read operation may be inresponse to, for example, a load instruction executed by processorcircuitry 12 of FIG. 1.

The first transforming circuitry 54 uses a system error coding functioncircuitry (TABLE S from FIG. 5) for full granularity (64-bit) errorcoding for generating a checkbit value for an N-bit data value. A firstinternal error coding function circuitry (TABLE 1 from FIG. 7) is forgenerating a checkbit value for an M-bit data value, where N is greaterthan M, and a cache index error coding function (TABLE B from FIG. 9) isused for generating a checkbit value for a cache index of the cache 14.Transforming circuitry 54 generates the checkbit values CACHE CHKBIT 0by applying the coding functions of TABLE 1, TABLE S, and TABLE B to theADDR and RDATA inputs and combines the resultant checkbit output valuesfrom each of these tables to form a final checkbit value. The secondtransforming circuitry 56 uses the system error coding functioncircuitry (TABLE S), second internal error coding function circuitry(TABLE 0) for generating a checkbit value for another M-bit data value,and the cache index error coding function circuitry (TABLE B). Thesecond internal error coding function circuitry using TABLE 0 implementsa different coding function than the first internal error codingfunction using TABLE 1 or the system error coding function circuitryusing TABLE S. Transforming circuitry 56 generates the checkbit valuesCACHE CHKBIT 1 by applying the coding functions of TABLE 0, TABLE S, andTABLE B to the ADDR and RDATA inputs and combines the resultant checkbitoutput values from each of these tables to form a final checkbit value.

FIG. 4 illustrates a portion of memory 38 or cache memory 14 of the dataprocessing system in accordance with an embodiment. A 64-bit entry inmemory 38 includes an even word portion D0 and an odd word portion D1.Each of portions D0 and D1 includes 32 bits of data. In anotherembodiment, the length of the entry may be different, and there may be adifferent number of portions. The entry also includes checkbits for D0and checkbits for D1. The checkbits are for 32-bit granularity. Thecheckbits for D0 are formed using TABLE 0 (FIG. 6) and the checkbits forD1 are formed using TABLE 1 (FIG. 7). An XOR gate 60 has inputsconnected to the checkbits for D0 and the checkbits for D1. An output ofXOR gate 60 provides checkbits for data words D0 plus D1 for 64-bitgranularity. An XOR gate 62 has an input connected to the output of XORgate 60 and an input connected to an address error coding functioncircuitry 66. The address error coding function circuitry 66 has aninput for receiving address A[0:28]. The address error coding functioncircuit 66 uses TABLE A from FIG. 8. A block 68 is provided forconcatenating D0 with D1. Block 68 has an output for providing eitherread data RDATA or write data WDATA which are 64-bit quantities.

In operation, cache 14 of processor 11 or memory storage 38 is accessed.The access may be to a first storage location having even word D0 and anadjacent second storage location having odd word D1. Each location has acheckbit value associated with it. The checkbit value of D0 and thecheckbit value of D1 are transformed into a new checkbit value at theoutput of XOR gate 60 which has full 64-bit granularity to cover theeven data word D0 combined with the odd data word D1, but has no addresscomponent. The final system checkbits corresponding to the codingfunction in TABLE S is formed at the output of XOR gate 62 by means ofanother transformation using the checkbit outputs of address errorcoding function circuitry 66 which uses TABLE A to provide the checkbitscorresponding to the address component A[0:28] of the combined D0 and D1data. The even data word D0 is concatenated with the odd data word D1and the new system checkbit values to be provided to system interconnect15 from either processor 11 on WDATA and WCHKBIT for the case where thecache is supplying data, for example, for a cache copyback operation, orfrom memory 17 on RDATA and RCHKBIT for the case of a memory 17 readoperation by processor 11.

FIG. 5 illustrates a 64-bit (full granularity) system checkbitgeneration table (TABLE S) in accordance with an embodiment. TABLE S isimplemented using a plurality of exclusive OR gates, where each XOR gateoutputs one corresponding bit value of a checkbit value. An asterisk (*)in a table entry indicates that the corresponding address and/or databits are used in an exclusive-OR (XOR) logic operation to form the finalcheckbit value on the left side of the table. The exclusive OR operationis a bit-by-bit, or bit-wise exclusive OR operation of the tableentries. For 64-bit granularity, the table section corresponding toD[0:31], D[32:63], and A[0:29] are combined using an exclusive ORoperation to provide a final value driven on the RCHKBIT[0:7] or WCHKBIT[0:7] outputs of the table. Note that the last three bits of the addressare not used because the address of a 64-bit doubleword only has 29 bitsin the illustrated embodiment.

FIG. 6 illustrates a 32-bit data checkbit generation table TABLE 0 foraddress bit A[29]=0 corresponding to an even word address. TABLE 0 isimplemented using a plurality of exclusive OR gates, where each XOR gateoutputs one corresponding bit value of a checkbit value. The exclusiveOR operation is a bit-by-bit, or bit-wise exclusive OR operation of thetable entries. TABLE 0 of FIG. 6 and TABLE 1 of FIG. 7 show the checkbitcodings used when 32-bit data granularity is needed, such as for storagein cache memory 14 or memory 17. The top half of TABLE 0 is for dataencoding and the bottom half is for address encoding. For 32-bitgranularity, TABLE 0 or TABLE 1 (depending on the word address beingeither even (A29=0) or odd (A29=1)) are used in transforming betweensystem checkbit encodings using a 64-bit granularity (TABLE S), andcache or memory 17 encodings using 32-bit granularity. The output ofeach table section is XOR'ed, then XOR'ed with the output of TABLE S,and then the intermediate result is again XOR'ed with the output ofTABLE B in FIG. 9 to provide the value used for internal checkbit valuesfor the cache or memory 17 (see FIG. 3). Note that in the illustratedembodiments, there are 29 address bits A[0:28]. The data portion ofTABLE 0 defines the checkbit coding function used for data when addressbit A29=0.

FIG. 7 illustrates a 32-bit data checkbit generation table TABLE 1 forA[29]=1 corresponding to an odd word address. TABLE 1 is implementedusing a plurality of exclusive OR gates, where each XOR gate outputs onecorresponding bit value of a checkbit value. The top half of TABLE 1 isfor data encoding and the bottom half is for address encoding. TABLE 1is used when address bit A29=1. The exclusive OR operation is abit-by-bit, or bit-wise exclusive OR operation of the table entries. Asdescribed for TABLE 0, transform circuitry 56 of FIG. 3 also utilizesthe outputs of TABLE S, TABLE 1, and TABLE B to provide values used forinternal checkbit values for the cache or memory 17. The data portion ofTABLE 1 defines the checkbit coding function used for data when addressbit A29=1.

FIG. 8 illustrates an address portion (TABLE A) of a checkbit generationtable in accordance with an embodiment. TABLE A is implemented using aplurality of exclusive OR gates, where each XOR gate outputs onecorresponding bit value of a checkbit value. TABLE A is the addressportion of checkbit generation of 64 or 32-bit ECC granularity. TABLE Ais used in conjunction with the portion of cache control 13 illustratedin FIG. 2 and in the process of FIG. 4. TABLE 0 and TABLE 1 (FIG. 6 andFIG. 7) show the checkbit coding used when 32-bit data granularity isselected. The exclusive OR operation is a bit-by-bit, or bit-wiseexclusive OR operation of the table entries.

FIG. 9 illustrates a cache index address portion (TABLE B) of a checkbitgeneration table in accordance with an embodiment. TABLE B isimplemented using a plurality of exclusive OR gates, where each XOR gateoutputs one corresponding bit value of a checkbit value. TABLE B is theaddress portion of checkbit generation of 32-bit ECC granularity used inthe cache, where only a cache index portion of the access address isused. TABLE B is used in conjunction with the portion of cache control13 illustrated in FIG. 2 and in the cache checkbit generation logicshown in FIG. 3. The exclusive OR operation is a bit-by-bit, or bit-wiseexclusive OR operation of the table entries. TABLE B is similar to TABLEA, but only includes those specific address bits that are used to indexinto the cache storage array that are not part of the cache TAG value.In the illustrated embodiment, address bits A[20:28] are used to indexthe cache to select one of 512 sets of cache ways. This address portionof the access address is sufficient to cover addressing errors which mayoccur internal to the cache array storage.

Because the apparatus implementing the present invention is, for themost part, composed of electronic components and circuits known to thoseskilled in the art, circuit details will not be explained in any greaterextent than that considered necessary as illustrated above, for theunderstanding and appreciation of the underlying concepts of the presentinvention and in order not to obfuscate or distract from the teachingsof the present invention.

Some of the above embodiments, as applicable, may be implemented using avariety of different information processing systems. For example,although FIG. 1 and the discussion thereof describe an exemplaryinformation processing architecture, this exemplary architecture ispresented merely to provide a useful reference in discussing variousaspects of the invention. Of course, the description of the architecturehas been simplified for purposes of discussion, and it is just one ofmany different types of appropriate architectures that may be used inaccordance with the invention. Those skilled in the art will recognizethat the boundaries between logic blocks are merely illustrative andthat alternative embodiments may merge logic blocks or circuit elementsor impose an alternate decomposition of functionality upon various logicblocks or circuit elements.

Thus, it is to be understood that the architectures depicted herein aremerely exemplary, and that in fact many other architectures can beimplemented which achieve the same functionality. In an abstract, butstill definite sense, any arrangement of components to achieve the samefunctionality is effectively “associated” such that the desiredfunctionality is achieved. Hence, any two components herein combined toachieve a particular functionality can be seen as “associated with” eachother such that the desired functionality is achieved, irrespective ofarchitectures or intermedial components. Likewise, any two components soassociated can also be viewed as being “operably connected,” or“operably coupled,” to each other to achieve the desired functionality.

Furthermore, those skilled in the art will recognize that boundariesbetween the functionality of the above described operations merelyillustrative. The functionality of multiple operations may be combinedinto a single operation, and/or the functionality of a single operationmay be distributed in additional operations. Moreover, alternativeembodiments may include multiple instances of a particular operation,and the order of operations may be altered in various other embodiments.

Although the invention is described herein with reference to specificembodiments, various modifications and changes can be made withoutdeparting from the scope of the present invention as set forth in theclaims below. Accordingly, the specification and figures are to beregarded in an illustrative rather than a restrictive sense, and allsuch modifications are intended to be included within the scope of thepresent invention. Any benefits, advantages, or solutions to problemsthat are described herein with regard to specific embodiments are notintended to be construed as a critical, required, or essential featureor element of any or all the claims.

The term “coupled,” as used herein, is not intended to be limited to adirect coupling or a mechanical coupling.

Furthermore, the terms “a” or “an,” as used herein, are defined as oneor more than one. Also, the use of introductory phrases such as “atleast one” and “one or more” in the claims should not be construed toimply that the introduction of another claim element by the indefinitearticles “a” or “an” limits any particular claim containing suchintroduced claim element to inventions containing only one such element,even when the same claim includes the introductory phrases “one or more”or “at least one” and indefinite articles such as “a” or “an.” The sameholds true for the use of definite articles.

Unless stated otherwise, terms such as “first” and “second” are used toarbitrarily distinguish between the elements such terms describe. Thus,these terms are not necessarily intended to indicate temporal or otherprioritization of such elements.

What is claimed is:
 1. In a data processing system having a processorand a memory coupled to the processor via a system interconnect, amethod comprising: initiating a read operation of a memory location; inresponse to the initiating the read operation, receiving a first datavalue and a first checkbit value corresponding to the first data valuefrom the memory location, wherein the first data value comprises a firstdata value portion and a second data value portion, each of the firstand second data value portions having fewer bits than the first datavalue; providing the first checkbit value to first transformingcircuitry and to second transforming circuitry, wherein the firsttransforming circuitry generates a second checkbit value correspondingto the first data value portion and the second transforming circuitrygenerates a third checkbit value corresponding to the second data valueportion; and storing the first data value portion with the secondcheckbit value in a first storage location and storing the second datavalue portion with the third checkbit value in a second storagelocation.
 2. The method of claim 1, further comprising: accessing thefirst data value portion and the second checkbit value; and using thesecond checkbit value and not the first checkbit value to check thefirst data value portion.
 3. The method of claim 1, further comprising:in response to the step of initiating the read operation, the memoryproviding the first data value and the second checkbit value to theprocessor via the system interconnect; and after the step of receivingthe first data value and the second checkbit value and prior to the stepof providing the first checking value to the first transformingcircuitry and the second transforming circuitry, performing, by theprocessor, end to end error detection by using the first checkbit valueto check the first data value.
 4. The method of claim 1, wherein each ofthe first and second storage locations are located within a cache memoryof the processor and the memory location is located in the memory, andwherein the step of initiating the read operation is performed inresponse to a cache miss or a cache fill.
 5. The method of claim 4,wherein: the first transforming circuitry uses system error codingfunction circuitry for generating a checkbit value for an N-bit datavalue, first internal error coding function circuitry for generating acheckbit value for an M-bit data value, and cache index error codingfunction circuitry for generating a checkbit value for a cache index ofthe cache; the second transforming circuitry uses the system errorcoding function circuitry, second internal error coding functioncircuitry for generating a checkbit value for the M-bit data value, andthe cache index error coding function circuitry; and the second internalerror coding function circuitry implements a different coding functionthan the first internal error coding function and N is greater than M,the first data value being an N-bit data value and each of the first andsecond data value portions being the M-bit data value.
 6. The method ofclaim 1, wherein: the first transforming circuitry uses system errorcoding function circuitry for generating a checkbit value for an N-bitdata value and first internal error coding function circuitry forgenerating a checkbit value for an M-bit data value; the secondtransforming circuitry uses the system error coding function circuitryand second internal error coding function circuitry for generating acheckbit value for an M-bit data value; and the second internal errorcoding function circuitry implements a different coding function thatthe first internal error coding function and N is greater than M, thefirst data value being an N-bit data value and each of the first andsecond data value portions being an M-bit data value.
 7. The method ofclaim 6, wherein: the system error coding function circuitry comprises afirst plurality of exclusive OR (XOR) gates, wherein each XOR gate ofthe first plurality of XOR gates outputs one corresponding bit value ofthe first checkbit value, and wherein each XOR gate of the firstplurality of XOR gates receives a predetermined subset of bit values ofthe first data value; the first internal error coding function circuitrycomprises a second plurality of XOR gates, wherein each XOR gate of thesecond plurality of XOR gates outputs one corresponding bit value of thethird checkbit value, and wherein each XOR gate of the second pluralityof XOR gates receives a predetermined subset of bit values of the seconddata value portion; and the second internal error coding functioncircuitry comprises a third plurality of XOR gates, wherein each XORgate of the third plurality of XOR gates outputs one corresponding bitvalue of the second checkbit value, and wherein each XOR gate of thethird plurality of XOR gates receives a predetermined subset of bitvalues of the first data value portion.
 8. A data processing systemcomprising: a memory to store a first data value in a memory location,and a first checkbit value corresponding to the first data value fromthe memory location; a processor configured to be in communication withthe memory via a system interconnect, the processor to initiate a readoperation of the memory location, in response to the read operationbeing initiated, to receive the first data value and the first checkbitvalue, wherein the first data value comprises a first data value portionand a second data value portion, each of the first and second data valueportions having fewer bits than the first data value; first transformingcircuitry configured to be in communication with the processor, thefirst transforming circuitry to receive the first checkbit value fromthe processor, and to generate a second checkbit value corresponding tothe first data value portion; and second transforming circuitryconfigured to be in communication with the processor, the secondtransforming circuitry to receive the first checkbit value from theprocessor, and to generate a third checkbit value corresponding to thesecond data value portion, the processor to store the first data valueportion with the second checkbit value in a first storage location, andto store the second data value portion with the third checkbit value ina second storage location.
 9. The data processing system of claim 8, theprocessor further to access the first data value portion and the secondcheckbit value, and use the second checkbit value and not the firstcheckbit value to check the first data value portion.
 10. The dataprocessing system of claim 8, wherein after the processor receives thefirst data value and the second checkbit value from the memory and priorto when the processor provides the first checking value to the firsttransforming circuitry and the second transforming circuitry, theprocessor to perform end to end error detection by using the firstcheckbit value to check the first data value.
 11. The data processingsystem of claim 8, wherein the processor initiates the read operation inresponse to a cache miss or a cache fill.
 12. The data processing systemof claim 11, wherein the first transforming circuitry comprises: systemerror coding function circuitry to generate a checkbit value for anN-bit data value; first internal error coding function circuitry togenerate a checkbit value for an M-bit data value; and cache index errorcoding function circuitry to generate a checkbit value for a cache indexof the cache;
 13. The data processing system of claim 12, wherein thesecond transforming circuitry comprises: second internal error codingfunction circuitry to generate a checkbit value for the M-bit datavalue, and wherein the second internal error coding function circuitryimplements a different coding function than the first internal errorcoding function and N is greater than M, the first data value being anN-bit data value and each of the first and second data value portionsbeing the M-bit data value.
 14. The data processing system of claim 8,wherein the first transforming circuitry comprises: system error codingfunction circuitry to generate a checkbit value for an N-bit data value;and first internal error coding function circuitry to generate acheckbit value for an M-bit data value;
 15. The data processing systemof claim 14, wherein the second transforming circuitry comprises: thesystem error coding function circuitry and second internal error codingfunction circuitry to generate a checkbit value for an M-bit data value,wherein the second internal error coding function circuitry implements adifferent coding function than the first internal error coding functionand N is greater than M, the first data value being an N-bit data valueand each of the first and second data value portions being an M-bit datavalue.
 16. The data processing system of claim 1, wherein: the systemerror coding function circuitry comprises a first plurality of exclusiveOR (XOR) gates, wherein each XOR gate of the first plurality of XORgates outputs one corresponding bit value of the first checkbit value,and wherein each XOR gate of the first plurality of XOR gates receives apredetermined subset of bit values of the first data value; the firstinternal error coding function circuitry comprises a second plurality ofXOR gates, wherein each XOR gate of the second plurality of XOR gatesoutputs one corresponding bit value of the third checkbit value, andwherein each XOR gate of the second plurality of XOR gates receives apredetermined subset of bit values of the second data value portion; andthe second internal error coding function circuitry comprises a thirdplurality of XOR gates, wherein each XOR gate of the third plurality ofXOR gates outputs one corresponding bit value of the second checkbitvalue, and wherein each XOR gate of the third plurality of XOR gatesreceives a predetermined subset of bit values of the first data valueportion.
 17. In a data processing system having a processor and a memorycoupled to the processor via a system interconnect, a method comprising:in response to a cache miss or a cache fill, receiving a first datavalue and a first checkbit value corresponding to the first data valuefrom the memory location, wherein the first data value comprises a firstdata value portion and a second data value portion; providing the firstcheckbit value to first transforming circuitry and to secondtransforming circuitry, wherein the first transforming circuitrygenerates a second checkbit value corresponding to the first data valueportion and the second transforming circuitry generates a third checkbitvalue corresponding to the second data value portion; storing the firstdata value portion with the second checkbit value in a first storagelocation of a cache memory of the processor; and storing the second datavalue portion with the third checkbit value in a second storage locationof the cache memory of the processor.
 18. The method of claim 17,further comprising: accessing the first data value portion and thesecond checkbit value; and using the second checkbit value and not thefirst checkbit value to check the first data value portion.
 19. Themethod of claim 17, wherein: the first transforming circuitry usessystem error coding function circuitry for generating a checkbit valuefor an N-bit data value and first internal error coding functioncircuitry for generating a checkbit value for an M-bit data value; thesecond transforming circuitry uses the system error coding functioncircuitry and second internal error coding function circuitry forgenerating a checkbit value for an M-bit data value; and the secondinternal error coding function circuitry implements a different codingfunction that the first internal error coding function and N is greaterthan M, the first data value being an N-bit data value and each of thefirst and second data value portions being an M-bit data value.
 20. Themethod of claim 19, wherein: the system error coding function circuitrycomprises a first plurality of exclusive OR (XOR) gates, wherein eachXOR gate of the first plurality of XOR gates outputs one correspondingbit value of the first checkbit value, and wherein each XOR gate of thefirst plurality of XOR gates receives a predetermined subset of bitvalues of the first data value; the first internal error coding functioncircuitry comprises a second plurality of XOR gates, wherein each XORgate of the second plurality of XOR gates outputs one corresponding bitvalue of the third checkbit value, and wherein each XOR gate of thesecond plurality of XOR gates receives a predetermined subset of bitvalues of the second data value portion; and the second internal errorcoding function circuitry comprises a third plurality of XOR gates,wherein each XOR gate of the third plurality of XOR gates outputs onecorresponding bit value of the second checkbit value, and wherein eachXOR gate of the third plurality of XOR gates receives a predeterminedsubset of bit values of the first data value portion.